RENESAS HD64F3062B HD64F3062BFBL25V Single Chip Microcomputer

RENESAS

HD64F3062BFBL25V

HD64F3062BFBL25V date sheet

Product category

Single Chip Microcomputer

Application

CPU

Specification

• Interrupt priority registers (IPRs) for setting interrupt priorities

Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis

in interrupt priority registers A and B (IPRA and IPRB).

• Three-level enabling/disabling by the I and UI bits in the CPU’s condition code register (CCR)

and the UE bit in the system control register (SYSCR)

• Seven external interrupt pins

NMI has the highest priority and is always accepted*; either the rising or falling edge can be

selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected

independently

Want know more us? Please check out  www.mjdic.com/