MPC8247VRMIBA PowerQUICC II Family
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PowerQUICC II Family |
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Application |
communications |
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Description |
The major features of the SoC are as follows: • Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 266–400 MHz — Separate 16 KB data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — Power Architecture®-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — Supports bus snooping for cache coherency |
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