AD ADSP 21062 ADSP 21062LKSZ SHARC Processor

Description

Image

40 MIPS, 25 ns instruction rate, single-cycle instruction

execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse

addressing)

Efficient program sequencing with zero-overhead looping:

Single-cycle loop setup

IEEE JTAG Standard 1149.1 Test Access Port and on-chip

emulation

32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data

format