XILINX XCV600E 7FG680C Field Programmable Gate Arrays

Description

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Fast, High-Density 1.8 V FPGA Family

- Densities from 58 k to 4 M system gates

- 130 MHz internal performance (four LUT levels)

- Designed for low-power operation

- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz

• Highly Flexible SelectI/O+™ Technology

- Supports 20 high-performance interface standards

- Up to 804 singled-ended I/Os or 344 differential I/O

pairs for an aggregate bandwidth of > 100 Gb/s

• Differential Signalling Support

- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

- Differential I/O signals can be input, output, or I/O

- Compatible with standard differential devices

- LVPECL and LVDS clock inputs for 300+ MHz clocks