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Features L High-Performance Static CMOS Technology 100 MHz (10-ns Cycle Time) 60 MHz (16.67-ns Cycle Time) Low-Power (1.8-V Core, 3.3-V I/O) Design JTAG Boundary Scan Support High-Performance 32-Bit CPU ( TMS320C28x™) 16 x 16 and 32 x 32 MAC Operations 16 x 16 Dual MAC Harvard Bus Architecture Atomic Operations Fast Interrupt Response and Processing Unified Memory Programming Model Code-Efficient (in C/C++ and Assembly) On-Chip Memory F2809: 128K x 16 Flash, 18K x 16 SARAM F2808: 64K x 16 Flash, 18K x 16 SARAM F2806: 32K x 16 Flash, 10K x 16 SARAM F2802: 32K x 16 Flash, 6K x 16 SARAM F2801: 16K x 16 Flash, 6K x 16 SARAM F2801x: 16K x 16 Flash, 6K x 16 SARAM |
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