TOSHIBA TC358860XBG CMOS Digital Integrated Circuit

Description

Image

Features

TC358860XBG follows the following standards:

MIPI Alliance Specification for Display Serial

Interface (DSI) version 1.1, Nov 22 2011

MIPI Alliance Specification for D-PHY Version

1.1, Nov 7 2011

VESA DisplayPort Standard version 1.2a, May

23 2012.

VESA Embedded DisplayPort Standard version

1.4 Feb. 28 2013

eDP Sink (Receiver)

Bit Rate @ 1.62, 2.16, 2.43, 2.7, 3.24, 4.32, 4.86

or 5.4Gbps, Voltage Swing @0.2 to 1.2 V,

Pre-Emphasis Level @3.5dB.

There are four lanes available in eDP main Link,

which can operate in 1-, 2- or 4-lane

configuration.

Support Single-Stream Transport (SST), not

multi-Stream Transport (MST)

Capable of Full and Fast Link Training

AUX channel with nominal bit rate at 1 Mbps.

Video input data formats supported: RGB666

and RGB888